System-on-Chip

System-on-Chip

NanoWatt SoC for System-in-Fiber

This work presents a fully autonomous system-on-chip (SoC) that can be distributed along a fiber strand, capable of simultaneously harvesting energy, cooperatively scaling performance, sharing power, and booting-up with other in-fiber SoCs for ultra-low-power (ULP) sensing applications. Utilizing a custom switched capacitor energy harvesting and power management unit (EHPMU), the SoC can efficiently redistribute and reuse harvested energy along the fiber. Integrated on-chip, the ULP RISC-V digital core and temperature sensor enable energy-efficient sensing and computation at nanowatt power levels. A dedicated ripple boot-up and cooperative dynamic voltage and frequency scaling (DVFS) further optimize the operation and physical size of the system. Fabricated in 65 nm, measurement results show that the proposed SoC achieves 33 nW power consumption for the whole chip under 92 Lux lighting condition and can reduce control power down to 2.7 nW for the EHPMU. With the proposed power sharing and cooperative DVFS techniques, the SoC reduces the illuminance needed to stay alive by >7× down to 12 Lux. Integrated into a mm-scale polymer fiber, our SoC demonstrates the feasibility of fully autonomous and ULP on-body sensing systems in resource-constrained fiber environments.

The proposed nanoWatt System-in-Fiber (NanoSiF) that supports distributed harvesting, sensing, processing and communication.

Sub-microWatt Scalable SoC

This work presents an ultra-low-power (ULP) internet-of-things (IoT) system-on-chip (SoC) using a triple-mode power management unit (PMU) to achieve self-adaptive power-performance scaling and energy-minimized operation. The proposed PMU comprises three modes: energy-aware mode, performance-aware mode, and minimum energy point (MEP) tracking mode. By controlling a microprocessor with the three modes, the SoC can adaptively scale its frequency and supply voltage based on either the input energy availability or the task priority. To achieve robust and rapid mode transitions, the SoC adopts fast dynamic voltage and frequency scaling (DVFS) and fast load transient response through asynchronous control. For energy-minimized operation, a sub-nW constant-energy-cycle algorithm keeps the microprocessor operating at the MEP with a 0.026 mm2 area overhead. In addition, the on-chip integration of a bias generator, clock, and power-on-reset block empowers the SoC to be a fully self-contained system. Fabricated in 65 nm CMOS, measurement results show that the SoC has a minimum power consumption of 194.3 nW at 180 Hz. The proposed PMU achieves 5.2 nW quiescent power and 92.6% peak efficiency meanwhile maintaining >80% efficiency from 190 nW to 3 mW. The MEPT circuits achieve <2.3% energy per cycle error and <18 mV voltage tracking error. The measured quiescent power of the MEPT circuits in the idle mode is 379 pW, which only accounts for 0.19% of the total system power. Measurements of the triple-mode transitions show that this SoC is well suited for resource-constrained IoT applications.

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